This blog series guides you through the foundations of RISC-V, an open source instruction set architecture (ISA) driving microcontrollers, laptops, and even supercomputers with support from thousands of organizations worldwide. RISC-V is not just a trend, but a developing integral part of future innovation. GPU giant NVIDIA shipped over 1 billion Falcon-class RISC-V cores in 2024. Other large companies, including Qualcomm, Google, and Bosch are also implementing RISC-V into their products. With RISC-V adoption only growing, now is the time to learn about this innovative technology.
To start your RISC-V journey, read the following articles that explain what RISC-V is and dives into how RISC-V works through hands-on, low-level examples.
From the Cradle to the OS: What’s an ISA?
This article doesn’t just give you the Google search definition of an ISA, it demonstrates the concept of an ISA through example processors to contextualize the RISC-V architecture.
From the Cradle to the OS 2: RISC-V Assembly
Follow a practical guide to set up the RISC-V toolchain, begin writing RISC-V assembly, and run a C program through clearly explained, easy steps.
From the Cradle to the OS 3: RISC-V Conventions
In this article, dive into RISC-V conditional branching and unconditional jumps to understand how a program navigates different execution paths. Also, learn how to debug a RISC-V program using the spike simulator’s debugging feature.
About the Author
I am an assistant professor of Computer Science and Software Engineering at the Rose-Hulman Institute of Technology. I was born in Kherbet Selem, a small village in southern Lebanon, attended college in Beirut, and then moved to the US to complete my PhD at the University of Illinois at Urbana-Champaign. My enjoyment of operating systems started early in my childhood, when formatting my tiny hard drive and reinstalling Windows 95 (multiple times a day) was the only way to get any video game to run on my aging PC; I might have enjoyed typing the fdisk command more than I did the games themselves!